/**
 * @file    gt9881_rcc.h
 * @author  Giantec-Semi ATE
 * @brief   CMSIS GT98xx Device Peripheral Access Layer Header File
 * @version 0.1
 * 
 * @copyright Copyright (c) 2021 Giantec-Semi
 * 
 */


#ifndef GT98XX_DEVICE_GT9881_RCC_H_
#define GT98XX_DEVICE_GT9881_RCC_H_

#ifdef __cplusplus
    extern "C" {
#endif /* __cplusplus */

#include "gt9881.h"

/**
 
 * @addtogroup Peripheral_Registers_Structures
 * @{
 */

/**
 * @struct ClkCtlRegTypedef
 * @brief  MCU Clock Control Registers structure definition
 */
typedef struct tagClkCtlRegTypedef {
  __IO uint32_t MCU_PLL_CFG;        ///< MCU PLL configuration and status register
  __IO uint32_t PLL_LK_CFG;         ///< MCU PLL lock configuration register
  __IO uint32_t MCU_CLK_CFG;        ///< MCU PLL clock configuration
  __IO uint32_t MCU_STCLK_CFG;      ///< Systick calibration register
  __IO uint32_t PWM_PLL_CFG;        ///< PWM PLL configuration and status register
  __IO uint32_t ANA_CLK_CFG;        ///< MCU clock configuration register
} ClkCtlRegTypedef;

typedef struct tagClkGatingCtlTypedef {
  __IO uint32_t MCU_BLK_CG;
}ClkGatingCtlTypedef;

/** @} Peripheral_Registers_Structures */

/**
 * @addtogroup Peripheral_Memory_Map
 * @{
 */
#define CLK_CTL_REG_BASE                (PERIPH_BASE + 0x00UL)           ///< MCU Clock Control Registers base address
#define CLK_CG_REG_BASE                 (PERIPH_BASE + 0x30UL)           ///< MCU Clock Gating Control Registers base address
/** @} Peripheral_Memory_Map */

/**
 * @addtogroup Peripheral_Declaration
 * @{
 */
#define CLK_CTL_REG               ((ClkCtlRegTypedef*)CLK_CTL_REG_BASE)    ///< MCU Clock Control Registers operator
#define CLK_CG_REG                ((ClkGatingCtlTypedef*)CLK_CG_REG_BASE)  ///< MCU Clock Gating Control Registers operator
/** @} Peripheral_Declaration */

/**
 * @defgroup CLOCK_CONTROL MCU Clock Control Registers
 * @ingroup  SYSREG
 * @brief    MCU Clock Control Registers
 * @{
 */

/**
 * @defgroup CLOCK_CONTROL_BITMAP MCU Clock Bitmap
 * @ingroup  CLOCK_CONTROL
 * @brief    Bitmap of Clock Control Registers
 * @{
 */

#define MCU_PLL_CFG_N_Pos                       (0U)    ///< Poision of MCU_PLL_CFG_N
#define MCU_PLL_CFG_N_Msk                       (0x3FUL << MCU_PLL_CFG_N_Pos)    ///< Bitmask of MCU_PLL_CFG_N
/**
 * @def   MCU_PLL_CFG_N
 * @brief PLL input divider N
 * <pre>
 * Default : 0x2 (96M)
 * </pre>
 */
#define MCU_PLL_CFG_N                           MCU_PLL_CFG_N_Msk

#define MCU_PLL_CFG_M_Pos                       (6U)    ///< Poision of MCU_PLL_CFG_M
#define MCU_PLL_CFG_M_Msk                       (0x3FUL << MCU_PLL_CFG_M_Pos)    ///< Bitmask of MCU_PLL_CFG_M
/**
 * @def   MCU_PLL_CFG_M
 * @brief PLL feedback divider M.
 * <pre>
 * Default : 0x30(96M)
 * </pre>
 */
#define MCU_PLL_CFG_M                           MCU_PLL_CFG_M_Msk

#define MCU_PLL_CFG_OD_Pos                      (12U)    ///< Poision of MCU_PLL_CFG_OD
#define MCU_PLL_CFG_OD_Msk                      (0x3UL << MCU_PLL_CFG_OD_Pos)    ///< Bitmask of MCU_PLL_CFG_OD
/**
 * @def   MCU_PLL_CFG_OD
 * @brief PLL output divider OD
 * <pre>
 * Default : 0x1(96M)
 * </pre>
 */
#define MCU_PLL_CFG_OD                          MCU_PLL_CFG_OD_Msk

#define MCU_PLL_CFG_BYP_Pos                     (14U)    ///< Poision of MCU_PLL_CFG_BYP
#define MCU_PLL_CFG_BYP_Msk                     (0x1UL << MCU_PLL_CFG_BYP_Pos)    ///< Bitmask of MCU_PLL_CFG_BYP
/**
 * @def   MCU_PLL_CFG_BYP
 * @brief PLL output divider OD
 * <pre>
 * @a 1'b1 : clock output comes from the PLL.
 * @a 1'b1 : PLL bypassed mode, FOUT=FIN/N
 * Default : 0
 * </pre>
 */
#define MCU_PLL_CFG_BYP                         MCU_PLL_CFG_BYP_Msk

#define MCU_PLL_CFG_PWDN_Pos                    (15U)    ///< Poision of MCU_PLL_CFG_PWDN
#define MCU_PLL_CFG_PWDN_Msk                    (0x1UL << MCU_PLL_CFG_PWDN_Pos)    ///< Bitmask of MCU_PLL_CFG_PWDN
/**
 * @def   MCU_PLL_CFG_PWDN
 * @brief PLL powder
 * <pre>
 * @a 1'b1 : PLL is power on
 * @a 1'b1 : PLL is power down
 * Default : 0
 * </pre>
 */
#define MCU_PLL_CFG_PWDN                        MCU_PLL_CFG_PWDN_Msk

#define MCU_PLL_CFG_EN_Pos                      (16U)    ///< Poision of MCU_PLL_CFG_EN
#define MCU_PLL_CFG_EN_Msk                      (0x1UL << MCU_PLL_CFG_EN_Pos)    ///< Bitmask of MCU_PLL_CFG_EN
/**
 * @def   MCU_PLL_CFG_EN
 * @brief PLL enable/disable
 * <pre>
 * @a 1'b1 : PLL disable
 * @a 1'b1 : PLL enable
 * Default : 1
 * </pre>
 */
#define MCU_PLL_CFG_EN                          MCU_PLL_CFG_EN_Msk

#define MCU_PLL_CFG_LK_EN_Pos                   (17U)    ///< Poision of MCU_PLL_CFG_LK_EN
#define MCU_PLL_CFG_LK_EN_Msk                   (0x1UL << MCU_PLL_CFG_LK_EN_Pos)    ///< Bitmask of MCU_PLL_CFG_LK_EN
/**
 * @def   MCU_PLL_CFG_LK_EN
 * @brief PLL enable/disable
 * <pre>
 * @a 1'b1 : N/A
 * @a 1'b1 : force the LOCK=1
 * Default : 0
 * </pre>
 */
#define MCU_PLL_CFG_LK_EN                       MCU_PLL_CFG_LK_EN_Msk

#define MCU_PLL_CFG_IN_SW_Pos                   (18U)    ///< Poision of MCU_PLL_CFG_IN_SW
#define MCU_PLL_CFG_IN_SW_Msk                   (0x1UL << MCU_PLL_CFG_IN_SW_Pos)    ///< Bitmask of MCU_PLL_CFG_IN_SW
/**
 * @def   MCU_PLL_CFG_IN_SW
 * @brief PLL clock
 * <pre>
 * @a 1'b1 : PLL input clk is OSC
 * @a 1'b1 : PLL input clk is external clk
 * Default : 0
 * </pre>
 */
#define MCU_PLL_CFG_IN_SW                       MCU_PLL_CFG_IN_SW_Msk

#define MCU_PLL_CFG_LOCK_Pos                    (30U)    ///< Poision of MCU_PLL_CFG_LOCK
#define MCU_PLL_CFG_LOCK_Msk                    (0x1UL << MCU_PLL_CFG_LOCK_Pos)    ///< Bitmask of MCU_PLL_CFG_LOCK
/**
 * @def   MCU_PLL_CFG_LOCK
 * @brief PLL_lock form PLL.Reflect the states of PLL signals of LOCK.
 */
#define MCU_PLL_CFG_LOCK                        MCU_PLL_CFG_LOCK_Msk

#define MCU_PLL_CFG_LOCKC_Pos                   (31U)    ///< Poision of MCU_PLL_CFG_LOCKC
#define MCU_PLL_CFG_LOCKC_Msk                   (0x1UL << MCU_PLL_CFG_LOCKC_Pos)    ///< Bitmask of MCU_PLL_CFG_LOCKC
/**
 * @def   MCU_PLL_CFG_LOCKC
 * @brief PLL_lock from Counter Reflect the states of PLL signals of LOCK.(512us delay)
 */
#define MCU_PLL_CFG_LOCKC                       MCU_PLL_CFG_LOCKC_Msk

#define PLL_LK_CFG_LOCK_COU_Pos                 (0U)    ///< Poision of PLL_LK_CFG_LOCK_COU
#define PLL_LK_CFG_LOCK_COU_Msk                 (0xFFFUL << PLL_LK_CFG_LOCK_COU_Pos)    ///< Bitmask of PLL_LK_CFG_LOCK_COU
/**
 * @def   PLL_LK_CFG_LOCK_COU
 * @brief Pll lock counter
 * <pre>
 * Default: 0xFFF(512us)
 * MAX    : 0xFFF(512us)
 * </pre>
 */
#define PLL_LK_CFG_LOCK_COU                     PLL_LK_CFG_LOCK_COU_Msk

#define MCU_CLK_CFG_APB_DIV_Pos                 (0U)    ///< Poision of MCU_CLK_CFG_APB_DIV
#define MCU_CLK_CFG_APB_DIV_Msk                 (0xFUL << MCU_CLK_CFG_APB_DIV_Pos)    ///< Bitmask of MCU_CLK_CFG_APB_DIV
/**
 * @def   MCU_CLK_CFG_APB_DIV
 * @brief Mcu apb clock
 * <pre>
 * Default: 0x01(1/2 of ahb_clk)
 * Mcu_apb_clk=ahb_clk/(bit[3:0]+1)
 * </pre>
 */
#define MCU_CLK_CFG_APB_DIV                     MCU_CLK_CFG_APB_DIV_Msk

#define MCU_CLK_CFG_AHB_DIV_Pos                 (4U)    ///< Poision of MCU_CLK_CFG_AHB_DIV
#define MCU_CLK_CFG_AHB_DIV_Msk                 (0xFUL << MCU_CLK_CFG_AHB_DIV_Pos)    ///< Bitmask of MCU_CLK_CFG_AHB_DIV
/**
 * @def   MCU_CLK_CFG_AHB_DIV
 * @brief Mcu ahb clock
 * <pre>
 * Default: 0x00(same as root_clk)
 * Mcu_ahb_clk=root_clk/(bit[3:0]+1)
 * </pre>
 */
#define MCU_CLK_CFG_AHB_DIV                     MCU_CLK_CFG_AHB_DIV_Msk

#define MCU_CLK_CFG_ROOT_DIV_Pos                (8U)    ///< Poision of MCU_CLK_CFG_ROOT_DIV
#define MCU_CLK_CFG_ROOT_DIV_Msk                (0x1UL << MCU_CLK_CFG_ROOT_DIV_Pos)    ///< Bitmask of MCU_CLK_CFG_ROOT_DIV
/**
 * @def   MCU_CLK_CFG_ROOT_DIV
 * @brief Mcu ahb clock
 * <pre>
 * Default: 0x00(same as clock_src)
 * root_clk=clock_src/(bit[0]+1)
 * </pre>
 */
#define MCU_CLK_CFG_ROOT_DIV                    MCU_CLK_CFG_ROOT_DIV_Msk

#define MCU_CLK_CFG_CLK_DIV_Pos                 (12U)    ///< Poision of MCU_CLK_CFG_CLK_DIV
#define MCU_CLK_CFG_CLK_DIV_Msk                 (0x7FUL << MCU_CLK_CFG_CLK_DIV_Pos)    ///< Bitmask of MCU_CLK_CFG_CLK_DIV
/**
 * @def   MCU_CLK_CFG_CLK_DIV
 * @brief test clock division
 * <pre>
 * Default: 0x00(same as test_clk_root)
 * test_clk_out=test_clk_root/(bit[6:0]+1)
 * </pre>
 */
#define MCU_CLK_CFG_CLK_DIV                     MCU_CLK_CFG_CLK_DIV_Msk

#define MCU_CLK_CFG_SOURCE_LV2_1_Pos            (25U)    ///< Poision of MCU_CLK_CFG_SOURCE_LV2_1
#define MCU_CLK_CFG_SOURCE_LV2_1_Msk            (0x1UL << MCU_CLK_CFG_SOURCE_LV2_1_Pos)    ///< Bitmask of MCU_CLK_CFG_SOURCE_LV2_1
/**
 * @def   MCU_CLK_CFG_SOURCE_LV2_1
 * @brief mcu_clk source level-2 selection control.
 * <pre>
 * @a 1'b0 : mcu_clk from 8M OSC or EXT CLK
 * @a 1'b1 : mcu_clk from MCU PLL or PWM PLL
 * Default: 0x00
 * </pre>
 */
#define MCU_CLK_CFG_SOURCE_LV2_1                MCU_CLK_CFG_SOURCE_LV2_1_Msk

#define MCU_CLK_CFG_SOURCE_LV1_1_Pos            (26U)    ///< Poision of MCU_CLK_CFG_SOURCE_LV1_1
#define MCU_CLK_CFG_SOURCE_LV1_1_Msk            (0x1UL << MCU_CLK_CFG_SOURCE_LV1_1_Pos)    ///< Bitmask of MCU_CLK_CFG_SOURCE_LV1_1
/**
 * @def   MCU_CLK_CFG_SOURCE_LV1_1
 * @brief mcu_clk source level-1 selection control.
 * <pre>
 * @a 1'b0 : mcu_clk from 8M OSC
 * @a 1'b1 : mcu_clk from EXT CLK
 * Default: 0x00
 * </pre>
 */
#define MCU_CLK_CFG_SOURCE_LV1_1                MCU_CLK_CFG_SOURCE_LV1_1_Msk

#define MCU_CLK_CFG_SOURCE_LV1_2_Pos            (27U)    ///< Poision of MCU_CLK_CFG_SOURCE_LV1_2
#define MCU_CLK_CFG_SOURCE_LV1_2_Msk            (0x1UL << MCU_CLK_CFG_SOURCE_LV1_2_Pos)    ///< Bitmask of MCU_CLK_CFG_SOURCE_LV1_2
/**
 * @def   MCU_CLK_CFG_SOURCE_LV1_2
 * @brief mcu_clk source level-1 selection control.
 * <pre>
 * @a 1'b0 : mcu_clk from MCU PLL(PLL1)
 * @a 1'b1 : mcu_clk from PWM PLL(PLL2)
 * Default: 0x00
 * </pre>
 */
#define MCU_CLK_CFG_SOURCE_LV1_2                MCU_CLK_CFG_SOURCE_LV1_2_Msk

#define MCU_CLK_CFG_SOURCE_Pos                  (28U)    ///< Poision of MCU_CLK_CFG_SOURCE
#define MCU_CLK_CFG_SOURCE_Msk                  (0x1UL << MCU_CLK_CFG_SOURCE_Pos)    ///< Bitmask of MCU_CLK_CFG_SOURCE
/**
 * @def   MCU_CLK_CFG_SOURCE
 * @brief pwm_clk source selection control.
 * <pre>
 * @a 1'b0 : pwm_clk from MCU PLL(PLL1)
 * @a 1'b1 : pwm_clk from PWM PLL(PLL2)
 * Default: 0x00
 * </pre>
 */
#define MCU_CLK_CFG_SOURCE                      MCU_CLK_CFG_SOURCE_Msk

#define MCU_CLK_CFG_SOURCE_LV2_2_Pos            (29U)    ///< Poision of MCU_CLK_CFG_SOURCE_LV2_2
#define MCU_CLK_CFG_SOURCE_LV2_2_Msk            (0x1UL << MCU_CLK_CFG_SOURCE_LV2_2_Pos)    ///< Bitmask of MCU_CLK_CFG_SOURCE_LV2_2
/**
 * @def   MCU_CLK_CFG_SOURCE_LV2_2
 * @brief test_clk source level-2 selection control.
 * <pre>
 * @a 1'b0 : test_clk from 8M OSC or EXT_CLK
 * @a 1'b1 : test_clk from PCLK
 * Default: 0x00
 * </pre>
 */
#define MCU_CLK_CFG_SOURCE_LV2_2                MCU_CLK_CFG_SOURCE_LV2_2_Msk

#define MCU_CLK_CFG_SOURCE_LV1_3_Pos            (30U)    ///< Poision of MCU_CLK_CFG_SOURCE_LV1_3
#define MCU_CLK_CFG_SOURCE_LV1_3_Msk            (0x1UL << MCU_CLK_CFG_SOURCE_LV1_3_Pos)    ///< Bitmask of MCU_CLK_CFG_SOURCE_LV1_3
/**
 * @def   MCU_CLK_CFG_SOURCE_LV1_3
 * @brief test_clk source level-1 selection control.
 * <pre>
 * @a 1'b0 : test_clk from 8M OSC
 * @a 1'b1 : test_clk from EXT_CLK
 * Default: 0x00
 * </pre>
 */
#define MCU_CLK_CFG_SOURCE_LV1_3                MCU_CLK_CFG_SOURCE_LV1_3_Msk

#define MCU_STCLK_CFG_INTEGER_VAL_Pos           (0U)    ///< Poision of MCU_STCLK_CFG_INTEGER_VAL
#define MCU_STCLK_CFG_INTEGER_VAL_Msk           (0xFFFFFFUL << MCU_CLK_CFG_INTEGER_VAL_Pos)    ///< Bitmask of MCU_STCLK_CFG_INTEGER_VAL
/**
 * @def   MCU_STCLK_CFG_INTEGER_VAL
 * @brief Provides an integer value to compute a 10ms (100Hz) delay from STCLK
 * <pre>
 * Default: 0
 * </pre>
 */
#define MCU_STCLK_CFG_INTEGER_VAL               MCU_STCLK_CFG_INTEGER_VAL_Msk

#define MCU_STCLK_CFG_SET_LOW_Pos               (24U)    ///< Poision of MCU_STCLK_CFG_SET_LOW
#define MCU_STCLK_CFG_SET_LOW_Msk               (0x1UL << MCU_STCLK_CFG_SET_LOW_Pos)    ///< Bitmask of MCU_STCLK_CFG_SET_LOW
/**
 * @def   MCU_STCLK_CFG_SET_LOW
 * @brief Set low if the system timer clock or the external reference clock, can guarantee an exact multiple of 10ms.
 * <pre>
 * Default: 0
 * </pre>
 */
#define MCU_STCLK_CFG_SET_LOW                   MCU_STCLK_CFG_SET_LOW_Msk

#define PWM_PLL_CFG_N_Pos                       (0U)    ///< Poision of PWM_PLL_CFG_N
#define PWM_PLL_CFG_N_Msk                       (0x3FUL << PWM_PLL_CFG_N_Pos)    ///< Bitmask of PWM_PLL_CFG_N
/**
 * @def   PWM_PLL_CFG_N
 * @brief PLL input divider N
 * <pre>
 * Default: 0x2 (100M)
 * </pre>
 */
#define PWM_PLL_CFG_N                           PWM_PLL_CFG_N_Msk

#define PWM_PLL_CFG_M_Pos                       (6U)    ///< Poision of PWM_PLL_CFG_M
#define PWM_PLL_CFG_M_Msk                       (0x3FUL << PWM_PLL_CFG_M_Pos)    ///< Bitmask of PWM_PLL_CFG_M
/**
 * @def   PWM_PLL_CFG_M
 * @brief PLL feedback divider M
 * <pre>
 * Default: 0x32 (100M)
 * </pre>
 */
#define PWM_PLL_CFG_M                           PWM_PLL_CFG_M_Msk

#define PWM_PLL_CFG_OD_Pos                      (12U)    ///< Poision of PWM_PLL_CFG_OD
#define PWM_PLL_CFG_OD_Msk                      (0x3UL << PWM_PLL_CFG_OD_Pos)    ///< Bitmask of PWM_PLL_CFG_OD
/**
 * @def   PWM_PLL_CFG_OD
 * @brief PLL output divider OD
 * <pre>
 * Default: 0x1 (100M)
 * </pre>
 */
#define PWM_PLL_CFG_OD                          PWM_PLL_CFG_OD_Msk

#define PWM_PLL_CFG_BYP_Pos                     (14U)    ///< Poision of PWM_PLL_CFG_BYP
#define PWM_PLL_CFG_BYP_Msk                     (0x1UL << PWM_PLL_CFG_BYP_Pos)    ///< Bitmask of PWM_PLL_CFG_BYP
/**
 * @def   PWM_PLL_CFG_BYP
 * @brief PLL bypassed mode
 * <pre>
 * @a 1'b0 : clock output comes from the PLL
 * @a 1'b1 : PLL bypassed mode, FOUT=FIN/N
 * Default: 0
 * </pre>
 */
#define PWM_PLL_CFG_BYP                         PWM_PLL_CFG_BYP_Msk

#define PWM_PLL_CFG_PWDN_Pos                    (15U)    ///< Poision of PWM_PLL_CFG_PWDN
#define PWM_PLL_CFG_PWDN_Msk                    (0x1UL << PWM_PLL_CFG_PWDN_Pos)    ///< Bitmask of PWM_PLL_CFG_PWDN
/**
 * @def   PWM_PLL_CFG_PWDN
 * @brief PLL power
 * <pre>
 * @a 1'b0 : PLL is power on
 * @a 1'b1 : PLL is power down
 * Default: 0
 * </pre>
 */
#define PWM_PLL_CFG_PWDN                        PWM_PLL_CFG_PWDN_Msk

#define PWM_PLL_CFG_EN_Pos                      (16U)    ///< Poision of PWM_PLL_CFG_EN
#define PWM_PLL_CFG_EN_Msk                      (0x1UL << PWM_PLL_CFG_EN_Pos)    ///< Bitmask of PWM_PLL_CFG_EN
/**
 * @def   PWM_PLL_CFG_EN
 * @brief PLL enable/disable
 * <pre>
 * @a 1'b0 : PLL disable
 * @a 1'b1 : PLL enable
 * Default: 1
 * </pre>
 */
#define PWM_PLL_CFG_EN                          PWM_PLL_CFG_EN_Msk

#define PWM_PLL_CFG_LK_EN_Pos                   (17U)    ///< Poision of PWM_PLL_CFG_LK_EN
#define PWM_PLL_CFG_LK_EN_Msk                   (0x1UL << PWM_PLL_CFG_LK_EN_Pos)    ///< Bitmask of PWM_PLL_CFG_LK_EN
/**
 * @def   PWM_PLL_CFG_LK_EN
 * @brief Lock enable
 * <pre>
 * @a 1'b0 : N/A
 * @a 1'b1 : force the LOCK=1
 * Default: 1
 * </pre>
 */
#define PWM_PLL_CFG_LK_EN                       PWM_PLL_CFG_LK_EN_Msk

#define PWM_PLL_CFG_IN_SW_Pos                   (18U)    ///< Poision of PWM_PLL_CFG_IN_SW
#define PWM_PLL_CFG_IN_SW_Msk                   (0x1UL << MCU_PLL_CFG_IN_SW_Pos)    ///< Bitmask of PWM_PLL_CFG_IN_SW
/**
 * @def   PWM_PLL_CFG_IN_SW
 * @brief PWM input clock switch
 * <pre>
 * @a 1'b0 : PLL input clk is OSC
 * @a 1'b1 : PLL input clk is external clk
 * Default: 0
 * </pre>
 */
#define PWM_PLL_CFG_IN_SW                       MCU_PLL_CFG_IN_SW_Msk

#define PWM_PLL_CFG_LOCK_Pos                    (30U)    ///< Poision of PWM_PLL_CFG_LOCK
#define PWM_PLL_CFG_LOCK_Msk                    (0x1UL << PWM_PLL_CFG_LOCK_Pos)    ///< Bitmask of PWM_PLL_CFG_LOCK
/**
 * @def   PWM_PLL_CFG_LOCK
 * @brief Reflect the states of PLL signals of LOCK.
 */
#define PWM_PLL_CFG_LOCK                        PWM_PLL_CFG_LOCK_Msk

#define PWM_PLL_CFG_LOCKC_Pos                   (31U)    ///< Poision of PWM_PLL_CFG_LOCKC
#define PWM_PLL_CFG_LOCKC_Msk                   (0x1UL << PWM_PLL_CFG_LOCKC_Pos)    ///< Bitmask of PWM_PLL_CFG_LOCKC
/**
 * @def   PWM_PLL_CFG_LOCKC
 * @brief PLL_lock from Counter. Read-only. Reflect the states of PLL signals of LOCK.(512us delay)
 */
#define PWM_PLL_CFG_LOCKC                       PWM_PLL_CFG_LOCKC_Msk

#define ANA_CLK_CFG_AF_CLK_DIV_Pos              (0U)    ///< Poision of ANA_CLK_CFG_AF_CLK_DIV
#define ANA_CLK_CFG_AF_CLK_DIV_Msk              (0xFFUL << ANA_CLK_CFG_AF_CLK_DIV_Pos)    ///< Bitmask of ANA_CLK_CFG_AF_CLK_DIV
/**
 * @def   ANA_CLK_CFG_AF_CLK_DIV
 * @brief AF clock division
 * <pre>
 * AF_clk = root_clk/(bit[7:0]+1)
 * Default: 0x7(1/8 of root_clk)
 * </pre>
 */
#define ANA_CLK_CFG_AF_CLK_DIV                  ANA_CLK_CFG_AF_CLK_DIV_Msk

#define ANA_CLK_CFG_ADC_CLK_DIV_Pos             (8U)    ///< Poision of ANA_CLK_CFG_ADC_CLK_DIV
#define ANA_CLK_CFG_ADC_CLK_DIV_Msk             (0xFFUL << ANA_CLK_CFG_ADC_CLK_DIV_Pos)    ///< Bitmask of ANA_CLK_CFG_ADC_CLK_DIV
/**
 * @def   ANA_CLK_CFG_ADC_CLK_DIV
 * @brief ADC clock division
 * <pre>
 * ADC_clk_div = root_clk/(bit[15:8]+1)
 * Default: 0x07(1/8 of root_clk)
 * </pre>
 */
#define ANA_CLK_CFG_ADC_CLK_DIV                 ANA_CLK_CFG_ADC_CLK_DIV_Msk

#define ANA_CLK_CFG_DAC_CLK_DIV_Pos             (16U)    ///< Poision of ANA_CLK_CFG_DAC_CLK_DIV
#define ANA_CLK_CFG_DAC_CLK_DIV_Msk             (0xFFUL << ANA_CLK_CFG_DAC_CLK_DIV_Pos)    ///< Bitmask of ANA_CLK_CFG_DAC_CLK_DIV
/**
 * @def   ANA_CLK_CFG_DAC_CLK_DIV
 * @brief DAC clock division
 * <pre>
 * DAC_clk_div = root_clk/(bit[23:16]+1)
 * Default: 0x07 (1/8 of root_clk)
 * </pre>
 */
#define ANA_CLK_CFG_DAC_CLK_DIV                 ANA_CLK_CFG_DAC_CLK_DIV_Msk

/** @} CLOCK_CONTROL_BITMAP */
/** @} CLOCK_CONTROL */

/**
 * @defgroup CLOCK_GATING_CONTROL MCU Clock Gating Control Register
 * @ingroup  SYSREG
 * @brief    MCU Clock Gating Control Register
 * @{
 */

/**
 * @defgroup CLOCK_GATING_CONTROL_BITMAP MCU Clock Gating Control Bitmap
 * @ingroup  CLOCK_GATING_CONTROL
 * @brief    Bitmap of  MCU Clock Gating Control Registers
 * @{
 */

#define MCU_BLK_CG_DMA_Pos                       (0U)    ///< Poision of MCU_BLK_CG_DMA
#define MCU_BLK_CG_DMA_Msk                       (0x1UL << MCU_BLK_CG_DMA_Pos)    ///< Bitmask of MCU_BLK_CG_DMA
/**
 * @def   MCU_BLK_CG_DMA
 * @brief DMA clock gating.
 * <pre>
 * @a 1'b0 : clock gating on the module
 * @a 1'b1 : clock gating off the module
 * </pre>
 */
#define MCU_BLK_CG_DMA                           MCU_BLK_CG_DMA_Msk

#define MCU_BLK_CG_EFC_Pos                       (1U)    ///< Poision of MCU_BLK_CG_EFC
#define MCU_BLK_CG_EFC_Msk                       (0x1UL << MCU_BLK_CG_EFC_Pos)    ///< Bitmask of MCU_BLK_CG_EFC
/**
 * @def   MCU_BLK_CG_EFC
 * @brief EFC clock gating.
 * <pre>
 * @a 1'b0 : clock gating on the module
 * @a 1'b1 : clock gating off the module
 * </pre>
 */
#define MCU_BLK_CG_EFC                           MCU_BLK_CG_EFC_Msk

#define MCU_BLK_CG_SRAM_Pos                      (2U)    ///< Poision of MCU_BLK_CG_SRAM
#define MCU_BLK_CG_SRAM_Msk                      (0x1UL << MCU_BLK_CG_SRAM_Pos)    ///< Bitmask of MCU_BLK_CG_SRAM
/**
 * @def   MCU_BLK_CG_SRAM
 * @brief SRAM clock gating.
 * <pre>
 * @a 1'b0 : clock gating on the module
 * @a 1'b1 : clock gating off the module
 * </pre>
 */
#define MCU_BLK_CG_SRAM                          MCU_BLK_CG_SRAM_Msk

#define MCU_BLK_CG_CORDIC_Pos                    (3U)    ///< Poision of MCU_BLK_CG_CORDIC
#define MCU_BLK_CG_CORDIC_Msk                    (0x1UL << MCU_BLK_CG_CORDIC_Pos)    ///< Bitmask of MCU_BLK_CG_CORDIC
/**
 * @def   MCU_BLK_CG_CORDIC
 * @brief CORDIC clock gating.
 * <pre>
 * @a 1'b0 : clock gating on the module
 * @a 1'b1 : clock gating off the module
 * </pre>
 */
#define MCU_BLK_CG_CORDIC                        MCU_BLK_CG_CORDIC_Msk

#define MCU_BLK_CG_SYSTIC_Pos                    (4U)    ///< Poision of MCU_BLK_CG_SYSTIC
#define MCU_BLK_CG_SYSTIC_Msk                    (0x1UL << MCU_BLK_CG_SYSTIC_Pos)    ///< Bitmask of MCU_BLK_CG_SYSTIC
/**
 * @def   MCU_BLK_CG_SYSTIC
 * @brief SYSTIC clock gating.
 * <pre>
 * @a 1'b0 : clock gating on the module
 * @a 1'b1 : clock gating off the module
 * </pre>
 */
#define MCU_BLK_CG_SYSTIC                        MCU_BLK_CG_SYSTIC_Msk

#define MCU_BLK_CG_UART_Pos                      (5U)    ///< Poision of MCU_BLK_CG_UART
#define MCU_BLK_CG_UART_Msk                      (0x1UL << MCU_BLK_CG_UART_Pos)    ///< Bitmask of MCU_BLK_CG_UART
/**
 * @def   MCU_BLK_CG_UART
 * @brief UART clock gating.
 * <pre>
 * @a 1'b0 : clock gating on the module
 * @a 1'b1 : clock gating off the module
 * </pre>
 */
#define MCU_BLK_CG_UART                          MCU_BLK_CG_UART_Msk

#define MCU_BLK_CG_SPI1_Pos                      (6U)    ///< Poision of MCU_BLK_CG_SPI1
#define MCU_BLK_CG_SPI1_Msk                      (0x1UL << MCU_BLK_CG_SPI1_Pos)    ///< Bitmask of MCU_BLK_CG_SPI1
/**
 * @def   MCU_BLK_CG_SPI1
 * @brief SPI1 clock gating.
 * <pre>
 * @a 1'b0 : clock gating on the module
 * @a 1'b1 : clock gating off the module
 * </pre>
 */
#define MCU_BLK_CG_SPI1                          MCU_BLK_CG_SPI1_Msk

#define MCU_BLK_CG_SPI2_Pos                      (7U)    ///< Poision of MCU_BLK_CG_SPI2
#define MCU_BLK_CG_SPI2_Msk                      (0x1UL << MCU_BLK_CG_SPI2_Pos)    ///< Bitmask of MCU_BLK_CG_SPI2
/**
 * @def   MCU_BLK_CG_SPI2
 * @brief SPI2 clock gating.
 * <pre>
 * @a 1'b0 : clock gating on the module
 * @a 1'b1 : clock gating off the module
 * </pre>
 */
#define MCU_BLK_CG_SPI2                          MCU_BLK_CG_SPI2_Msk

#define MCU_BLK_CG_I2C1_Pos                      (8U)    ///< Poision of MCU_BLK_CG_I2C1
#define MCU_BLK_CG_I2C1_Msk                      (0x1UL << MCU_BLK_CG_I2C1_Pos)    ///< Bitmask of MCU_BLK_CG_I2C1
/**
 * @def   MCU_BLK_CG_I2C1
 * @brief I2C1 clock gating.
 * <pre>
 * @a 1'b0 : clock gating on the module
 * @a 1'b1 : clock gating off the module
 * </pre>
 */
#define MCU_BLK_CG_I2C1                          MCU_BLK_CG_I2C1_Msk

#define MCU_BLK_CG_I2C2_Pos                      (9U)    ///< Poision of MCU_BLK_CG_I2C2
#define MCU_BLK_CG_I2C2_Msk                      (0x1UL << MCU_BLK_CG_I2C2_Pos)    ///< Bitmask of MCU_BLK_CG_I2C2
/**
 * @def   MCU_BLK_CG_I2C2
 * @brief I2C2 clock gating.
 * <pre>
 * @a 1'b0 : clock gating on the module
 * @a 1'b1 : clock gating off the module
 * </pre>
 */
#define MCU_BLK_CG_I2C2                          MCU_BLK_CG_I2C2_Msk

#define MCU_BLK_CG_IWDT_Pos                      (10U)    ///< Poision of MCU_BLK_CG_IWDT
#define MCU_BLK_CG_IWDT_Msk                      (0x1UL << MCU_BLK_CG_IWDT_Pos)    ///< Bitmask of MCU_BLK_CG_IWDT
/**
 * @def   MCU_BLK_CG_IWDT
 * @brief IWDT clock gating.
 * <pre>
 * @a 1'b0 : clock gating on the module
 * @a 1'b1 : clock gating off the module
 * </pre>
 */
#define MCU_BLK_CG_IWDT                          MCU_BLK_CG_IWDT_Msk

#define MCU_BLK_CG_TIMER_Pos                     (11U)    ///< Poision of MCU_BLK_CG_TIMER
#define MCU_BLK_CG_TIMER_Msk                     (0x1UL << MCU_BLK_CG_TIMER_Pos)    ///< Bitmask of MCU_BLK_CG_TIMER
/**
 * @def   MCU_BLK_CG_TIMER
 * @brief TIMER clock gating.
 * <pre>
 * @a 1'b0 : clock gating on the module
 * @a 1'b1 : clock gating off the module
 * </pre>
 */
#define MCU_BLK_CG_TIMER                         MCU_BLK_CG_TIMER_Msk

#define MCU_BLK_CG_GPIO_Pos                      (12U)    ///< Poision of MCU_BLK_CG_GPIO
#define MCU_BLK_CG_GPIO_Msk                      (0x1UL << MCU_BLK_CG_GPIO_Pos)    ///< Bitmask of MCU_BLK_CG_GPIO
/**
 * @def   MCU_BLK_CG_GPIO
 * @brief GPIO clock gating.
 * <pre>
 * @a 1'b0 : clock gating on the module
 * @a 1'b1 : clock gating off the module
 * </pre>
 */
#define MCU_BLK_CG_GPIO                          MCU_BLK_CG_GPIO_Msk

#define MCU_BLK_CG_RINGBUFFER_Pos                (13U)    ///< Poision of MCU_BLK_CG_RINGBUFFER
#define MCU_BLK_CG_RINGBUFFER_Msk                (0x1UL << MCU_BLK_CG_RINGBUFFER_Pos)    ///< Bitmask of MCU_BLK_CG_RINGBUFFER
/**
 * @def   MCU_BLK_CG_RINGBUFFER
 * @brief RINGBUFFER clock gating.
 * <pre>
 * @a 1'b0 : clock gating on the module
 * @a 1'b1 : clock gating off the module
 * </pre>
 */
#define MCU_BLK_CG_RINGBUFFER                    MCU_BLK_CG_RINGBUFFER_Msk

#define MCU_BLK_CG_PMU_Pos                      (14U)    ///< Poision of MCU_BLK_CG_PMU
#define MCU_BLK_CG_PMU_Msk                      (0x1UL << MCU_BLK_CG_PMU_Pos)    ///< Bitmask of MCU_BLK_CG_PMU
/**
 * @def   MCU_BLK_CG_I2C3
 * @brief I2C3 clock gating.
 * <pre>
 * @a 1'b0 : clock gating on the module
 * @a 1'b1 : clock gating off the module
 * </pre>
 */
#define MCU_BLK_CG_PMU                          MCU_BLK_CG_PMU_Msk

#define MCU_BLK_CG_ADC_Pos                       (15U)    ///< Poision of MCU_BLK_CG_ADC
#define MCU_BLK_CG_ADC_Msk                       (0x1UL << MCU_BLK_CG_ADC_Pos)    ///< Bitmask of MCU_BLK_CG_ADC
/**
 * @def   MCU_BLK_CG_ADC
 * @brief ADC clock gating.
 * <pre>
 * @a 1'b0 : clock gating on the module
 * @a 1'b1 : clock gating off the module
 * </pre>
 */
#define MCU_BLK_CG_ADC                           MCU_BLK_CG_ADC_Msk

#define MCU_BLK_CG_XDAC_Pos                      (16U)    ///< Poision of MCU_BLK_CG_XDAC
#define MCU_BLK_CG_XDAC_Msk                      (0x1UL << MCU_BLK_CG_XDAC_Pos)    ///< Bitmask of MCU_BLK_CG_XDAC
/**
 * @def   MCU_BLK_CG_XDAC
 * @brief XDAC clock gating.
 * <pre>
 * @a 1'b0 : clock gating on the module
 * @a 1'b1 : clock gating off the module
 * </pre>
 */
#define MCU_BLK_CG_XDAC                          MCU_BLK_CG_XDAC_Msk

#define MCU_BLK_CG_YDAC_Pos                      (17U)    ///< Poision of MCU_BLK_CG_YDAC
#define MCU_BLK_CG_YDAC_Msk                      (0x1UL << MCU_BLK_CG_YDAC_Pos)    ///< Bitmask of MCU_BLK_CG_YDAC
/**
 * @def   MCU_BLK_CG_YDAC
 * @brief YDAC clock gating.
 * <pre>
 * @a 1'b0 : clock gating on the module
 * @a 1'b1 : clock gating off the module
 * </pre>
 */
#define MCU_BLK_CG_YDAC                          MCU_BLK_CG_YDAC_Msk

#define MCU_BLK_CG_AFDAC_Pos                     (18U)    ///< Poision of MCU_BLK_CG_AFDAC
#define MCU_BLK_CG_AFDAC_Msk                     (0x1UL << MCU_BLK_CG_AFDAC_Pos)    ///< Bitmask of MCU_BLK_CG_AFDAC
/**
 * @def   MCU_BLK_CG_AFDAC
 * @brief AFDAC clock gating.
 * <pre>
 * @a 1'b0 : clock gating on the module
 * @a 1'b1 : clock gating off the module
 * </pre>
 */
#define MCU_BLK_CG_AFDAC                         MCU_BLK_CG_AFDAC_Msk

#define MCU_BLK_CG_AFC_Pos                       (19U)    ///< Poision of MCU_BLK_CG_AFC
#define MCU_BLK_CG_AFC_Msk                       (0x1UL << MCU_BLK_CG_AFC_Pos)    ///< Bitmask of MCU_BLK_CG_AFC
/**
 * @def   MCU_BLK_CG_AFC
 * @brief AFC clock gating.
 * <pre>
 * @a 1'b0 : clock gating on the module
 * @a 1'b1 : clock gating off the module
 * </pre>
 */
#define MCU_BLK_CG_AFC                           MCU_BLK_CG_AFC_Msk

#define MCU_BLK_CG_MISC_Pos                      (20U)    ///< Poision of MCU_BLK_CG_MISC
#define MCU_BLK_CG_MISC_Msk                      (0x1UL << MCU_BLK_CG_MISC_Pos)    ///< Bitmask of MCU_BLK_CG_MISC
/**
 * @def   MCU_BLK_CG_MISC
 * @brief MISC clock gating.
 * <pre>
 * @a 1'b0 : clock gating on the module
 * @a 1'b1 : clock gating off the module
 * </pre>
 */
#define MCU_BLK_CG_MISC                          MCU_BLK_CG_MISC_Msk

#define MCU_BLK_CG_PWM_Pos                       (21U)    ///< Poision of MCU_BLK_CG_PWM
#define MCU_BLK_CG_PWM_Msk                       (0x1UL << MCU_BLK_CG_PWM_Pos)    ///< Bitmask of MCU_BLK_CG_PWM
/**
 * @def   MCU_BLK_CG_PWM
 * @brief PWM clock gating.
 * <pre>
 * @a 1'b0 : clock gating on the module
 * @a 1'b1 : clock gating off the module
 * </pre>
 */
#define MCU_BLK_CG_PWM                           MCU_BLK_CG_PWM_Msk

/** @} CLOCK_GATING_CONTROL_BITMAP */
/** @} CLOCK_GATING_CONTROL */

#define IS_RCC_INSTANCE(INSTANCE)         ((INSTANCE) == CLK_CTL_REG)

#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif /* GT98XX_DEVICE_GT9881_SYSCTRL_H_ */
